CHENNAI: A two-day workshop, RISC-V, on software and hardware innovators, opened at IIT Madras on Wednesday. The workshop is aimed to deliver free, extensible software and hardware freedom on architecture, paving way for the next 50 years of computing design and innovation.
RISC-V is a free and open Instruction Set Architecture (ISA) that enables a new era of processor innovation through open standard collaboration. The conference is organised by RISC-V Foundation, founded in 2015. It comprises more than 100-member organisations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward.
Workshop vice-chair Kamakoti Veezhinathan, professor, Computer Science and Engineering Department, IIT Madras, said, “The National Microprocessor Development Program, funded by Ministry of Electronics and Information Technology, Government of India, aims to develop indigenous microprocessor for the country. The processor code being developed as part of this programme is based on RISC-V ISA.”
The RISC-V Foundation has a board of directors comprising seven representatives from Bluespec, Inc., Google, Microsemi, NVIDIA, NXP, University of California, Berkeley, and Western Digital.
Kamakoti said that open source architecture was important in the digital world. Different organisations required different types of processing elements and computing powers. These should be quickly configurable to suit a company’s or country’s requirements. “These companies and countries need a good software support for the hardware they develop. In this context, an open source extensible instruction set architecture is of utmost necessity.”